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ds07-12561-1e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89202 series mb89202/f202/v201 description the mb89202 series is a line of single-chip microcontrollers . in addition to a compact instruction set, the micro- controllers contain a variety of peripheral functions su ch, timers, a serial interface, an a/d converter and an external interrupt. features ?f 2 mc-8l family cpu core maximum memory space : 64 kbytes minimum execution time : 0.32 s/12.5 mhz interrupt processing time : 2.88 s/12.5 mhz i/o ports : max 26 channels 21-bit time-base timer 8-bit pwm timer 8/16-bit capture timer/counter 10-bit a/d converter : 8 channels uart 8-bit serial i/o external interrupt 1 : 3 channels external interrupt 2 : 8 channels wild register : 2 bytes (continued) packages 32-pin plastic sh-dip 34-pin plastic ssop (dip-32p-m06) (fpt-34p-m03)
mb89202 series 2 (continued) mb89f202 : flash (at least 10,000 progra m / erase cycles) with read protection low-power consumption modes ( sleep mode, and stop mode) sh-dip-32, ssop-34 package cmos technology product lineup (continued) part number mb89202 mb89f202 mb89v201 parameter classification mask rom product flash memory product (read protection) evaluation product (for development) rom size 16 k 8 bits (internal mask rom) 16 k 8 bits (internal flash) 32k x 8 bits (external eprom) ram size 512 8 bits cpu functions number of instructions : instruction bit length : instruction length : data bit length : minimum execution time : interrupt processing time : 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.32 s to 5.1 s (12.5 mhz) 2.88 s to 46.1 s (12.5 mhz) ports general-purpose i/o ports (cmos) : 26 (also serve as peripherals ) (4 ports are also an n-ch open-drain type.) 21-bit time-base timer 21-bit interrupt cycle : 0.66 ms, 2.64 ms, 21 ms, or 335.5 ms with 12.5 mhz main clock watchdog timer reset generation cycle : 335.5 ms minimum with 12.5 mhz main clock 8-bit pwm timer 8-bit interval timer operation (square output capable, operating clock cycle : 0.32 s , 2.56 s, 5.1 s, 20.5 s) 8-bit resolution pwm operation (conversion cycle : 81.9 s to 21.47 s : in the selection of internal shift clock of 8/16-bit capture timer) count clock selectable between 8-bit and 16-bit timer/counter outputs 8/16-bit capture, timer/counter 8-bit capture timer/counter 1 channel + 8-bit timer or 16-bit capture timer/counter 1 channel capable of event count operati on and square wave output using external clock input with 8-bit timer 0 or 16-bit counter uart transfer data length : 6/7/8 bits 8-bit serial i/o 8 bits lsb first/msb first selectable one clock selectable from four operation clocks (one external shift clock, three internal shift clocks : 0.8 s, 6.4 s, 25.6 s) 12-bit ppg timer output frequency : pulse width and cycle selectable external interrupt 1 (wake-up function) 3 channels (interrupt vector, req uest flag, request output enabled) edge selectable (rising edge, falling edge, or both edges) also available for resetting stop/sleep mode (edge detectable even in stop mode) external interrupt 2 (wake-up function) 1 channel with 8 inputs (independent l- level interrupt and input enable) also available for resetting stop/sleep mode (level detectable even in stop mode)
mb89202 series 3 (continued) *1 : check section ? mask options? *2 : the minimum operating voltage varies with the operat ing frequency, the function, a nd the connected ice. (the operating voltage of the a/d converter is assured separately. check section ? electrical character- istics.?) package and corresponding products : available : not available differences among products ? memory size before evaluating using the evaluation product, verify it s differences from the product that will actually be used. mask options functions that can be selected as options and how to de signate these options vary by the product. before using options check section ? mask options?. part number mb89202 mb89f202 mb89v201 parameter 10-bit a/d converter 10-bit precision 8 channels a/d conversion function (conversion time : 12.16 s/12.5 mhz) continuous activation by 8/16-bit timer/co unter output or time-base timer counter wild register 8-bit 2 standby mode sleep mode, and stop mode overhead time from reset to the first instruction execution power-on reset : oscillation stabillization wait* 1 external reset : a few s software reset : a few s power-on reset : voltage regulator and oscillation stabillization wait (31.5 ms/12.5 mhz) external reset : oscillation stabillization wait (21.0 ms/12.5 mhz) software reset : a few s power-on reset : oscillation stabillization wait (21.0 ms / 12.5 mhz) external reset : oscillation stabillization wait (21.0 ms / 12.5 mhz) software reset : a few s power supply voltage* 2 2.2 v to 5.5 v 3.5 v to 5.5 v 2.7 v to 5.5 v package mb89202 mb89f202 mb89v201 dip-32p-m06 fpt-34p-m03 fpt-64p-m03
mb89202 series 4 pin assignments (continued) (top view) (dip-32p-m06) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v cc p03/int23/an 7 p02/int22/an 6 p01/int21/an 5 p00/int20/an 4 p43/an3* p42/an2* p41/an1* p40/an0* p72* p71* p70* p50/pwm p30/uck/sck p31/uo/so p32/ui/si 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p04/int24 p05/int25 p06/int26 p07/int27 p60 p61 rst x0 x1 v ss p37/bz/ppg p36/int12 p35/int11 p 34/to/int10 p33/ec c * : large-current drive type
mb89202 series 5 (continued) (top view) * : large-current drive type n.c. : internally connected. do not use. (fpt-34p-m03) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 p04/int24 p05/int25 p06/int26 p07/int27 p60 p61 rst x0 x1 v ss p37/bz/ppg p36/int12 p35/int11 p34/to/int10 n.c. p33/ec p32/ui/si p31/uo/so p30/uck/sck p50/pwm n.c. c p70 * p71 * p72 * p40/an0 * p41/an1 * p42/an2 * p43/an3 * p00/int20/an4 p01/int21/an5 p02/int22/an6 p03/int23/an7 v cc
mb89202 series 6 pin description (continued) pin no. pin name circuit type function sh-dip32* 1 ssop34* 2 88 x0 a pins for connecting the crystal for t he main clock. to use an external clock, input the signal to x0 and leave x1 open. 99 x1 5, 6 5, 6 p60, p61 h / e general-purpose cmos input port for mb89f202. general-puspose cmos i/o port for mb89202/mb89v201. 77 rst c reset i/o pin. this pin serves as an n-channel open-drain reset output with pull-up resistor (not available for mb89f202 ) and a reset input as well. the reset is a hysteresis input. it outputs the ?l? signal in response to an internal reset request. also, it initializes the internal circuit upon input of the ?l? signal. 28 to 31 30 to 33 p00/int20 / an4 to p03/ int23 /an7 g general-purpose cmos i/o ports. these pins also serve as an input (wake-up input) of external interrupt 2 or as an 10-bit a/d converter analog input. the input of external in- terrupt 2 is a hysteresis input. 1 to 4 1 to 4 p04/int24 to p07/int27 d general-purpose cmos i/o ports. these pins also serve as an input (wake-up input) of external interrupt 2. the input of external inte rrupt 2 is a hysteresis input. 19 20 p30/uck/ sck b general-purpose cmos i/o ports. this pin also serves as the clock i/o pin for the uart or 8-bit serial i/o. the resource is a hysteresis input. 18 19 p31/uo/so e general-purpose cmos i/o ports. this pin also serves as the data outp ut pin for the uart or 8-bit serial i/o. 17 18 p32/ui/si b general-purpose cmos i/o ports. this pin also serves as the data input pin for the uart or 8-bit serial i/o. the resource is a hysteresis input. 15 15 p33/ec b general-purpose cmos i/o ports. this pin also serves as the external clock input pin for the 8/16-bit cap- ture timer/counter. the resource is a hysteresis input. 14 14 p34/to/ int10 b general-purpose cmos i/o ports. this pin also serves as the output pin for the 8/16-bit capture timer/ counter or as the input pin for extern al interrupt 1. the resource is a hysteresis input. 13, 12 13, 12 p35/int11, p36/int12 b general-purpose cmos i/o ports. these pins also serve as the input pi n for external interrupt 1. the re- source is a hysteresis input. 11 11 p37/bz/ ppg e general-purpose cmos i/o ports. this pin also serves as the buzzer output pin or the 12-bit ppg output. 20 21 p50/pwm e general-purpose cmos i/o ports. this pin also serves as the 8-bit pwm timer output pin.
mb89202 series 7 (continued) *1 : dip-32p-m06 *2 : fpt-34p-m03 pin no. pin name circuit type function sh-dip32* 1 ssop34* 2 24 to 27 26 to 29 p40/an0 to p43/ an3 f general-purpose cmos i/o ports. these pins can also be used as n-channel open-drain ports. these pins also serve as 10-bit a/d converter analog input pins. 21 to 23 23 to 25 p70 to p72 e general-purpose cmos i/o ports. 32 34 v cc ? power supply pin 10 10 v ss ? power (gnd) pin 16 17 c ? mb89f202: capacitance pin for regu lating the power supply. connect an external ceramic capacitor of about 0.1 f. mb89202: this pin is not internally connect ed. it is unnecessary to connect a capacitor. ? 16, 22 n.c. ? internally connected pins be sure to leave it open.
mb89202 series 8 i/o circuit type (continued) type circuit remarks a at an oscillation feedback resistance of approximately 500 k ? b cmos output hysteresis input pull-up resistor optional c at an output pull-up resister (p-ch) of approximately 50 k ? /5.0 v (not available for mb89f202) n-ch open-drain reset output hysteresis input d cmos output cmos input hysteresis input (resource input) pull-up resistor optional x1 standby control signal x0 p-ch n-ch p-ch i nput enable port input / resource inp ut p-ch (not available for mb89f20 2) n-ch reset p-ch n-ch p-ch i nput enable i nput enable port input resource inp ut
mb89202 series 9 (continued) type circuit remarks e cmos output cmos input pull-up resistor optional p70-p72 are large-current drive type f cmos output cmos input analog input n-ch open-drain output available p40-p43 are large-current drive type g cmos output cmos input hysteresis input (resource input) analog input h cmos input p-ch n-ch p-ch i nput enable port inp ut p-ch open-drain control analog input a/d enable n-ch i nput enable port inp ut p-ch analog input a/d enable n-ch p-ch i nput enable i nput enable port input resource inp ut i nput enable port inp ut
mb89202 series 10 handling devices preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on ?1. absolute maximum ratings? in section ? electrical characteristics? is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. treatment of unused input pins leaving unused input terminals open may lead to per manent damage due to malf unction and latchup; pull up or pull down the terminals through the resistors of 2 k ? or more. make the unused i/o terminal in a state of output and leave it open or if it is in an input state, handle it with the same procedure as the input terminals. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rate d range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10 % of the standard v cc value at the commercial fre quency (50 hz to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode. about the wild register function no wild register can be debugged on th e mb89v201. for the operation chec k, test the mb89f202 installed on a target system. program execution in ram when the mb89v201 is used, no program can be executed in ram. note to noise in the external reset pin (rst ) if the reset pulse applied to the external reset pin (rst ) does not meet the specific ations, it may cause malfunc- tions. use caution so that the reset pul se less than the specifications will not be fed to the external reset pin (rst ). external pullup for the external reset pin (rst ) of mb89f202 internal pullup control for rst pin is not available for mb89f202. to en sure proper external reset control in mb89f202, an external pullup (recommend 100 k ? ) for rst pin must be required. (continued)
mb89202 series 11 (continued) notes on selecting mask option please select ?with reset output? by the mask option when power-on reset is generated at the power supply on, and the device is used without inputting external reset.
mb89202 series 12 programming and erase flash memory on the mb89f202 1. flash memory the flash memory is located between c000 h and ffff h in the cpu memory map and incorporates a flash memory interface circuit that allows read access and pr ogram access from the cpu to be performed in the same way as mask rom. programming and erasing flash memory is also performed via the flash memory interface circuit by executing instructions in the cpu. this e nables the flash memory to be updated in place under the control of the cpu, providing an efficient method of updating program and data. 2. flash memory features 16 k byte 8-bit configuration automatic programming algorithm (embedded algorithm*) data polling and toggle bit for detection of program/erase completion detection of program/erase completion via cpu interrupt compatible with jedec-standard commands no. of program / erase cycles : minimum 10,000 * : embedded algorithm is a tradem ark of advanced micro devices. 3. procedure for programming and erasing flash memory programming and reading flash memory cannot be performed at the same time. accordingly, to program or erase flash memory, the program must first be copied fr om flash memory to ram so that programming can be performed without program access from flash memory. 4. flash memory control status register (fmcs) 5. memory space the memory space for the cpu access and for the flash programmer access is listed below. 6. flash programmer adapter and recommended flash programmers ? parallel programmer * : for the programmer and the version of the pr ogrammer,contact the flash support group, inc. inquiry : flash support group, inc. : fax : 81-(53)-428-8377 : e-mail : support@j-fsg.co.jp ? serial programmer (pc programmer) inquiries : adapter : sunhayato corp. : fax : 81-(3)-3971-0535 e-mail : adapter@sunhayato.co.jp pc programmer software : fujitsu limited memory size cpu address programmer address 16 k bytes ffff h to c000 h ffff h to c000 h part number package adapter part number programmer part number * mb89f202p-sh dip-32p-m06 tef200-89f202-psh af9708, af9709/b, af9723 + af9834 mb89f202pfv fpt-34p-m03 tef200-89f202-pfv part number package adapter part number mb89f202p-sh dip-32p-m06 rom3-dip32pm06-8l mb89f202pfv fpt-34p-m03 rom3-fpt34pm03-8l inte rdyint we rdy bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r address 0079 h initial valu e 000x---- b
mb89202 series 13 7. flash content protection flash content can be read using parallel / serial progra mmer if the flash content protection mechanism is not activated. one predefined area of the flash (fffc h ) is assigned to be used for preventi ng the read access of flash content. if the protection code "01 h " is written in this address (fffc h ), the flash content cannot be read by any parallel/ serial programmer. note : the program written into the flash cannot be ve rified once the flash protection code is written ("01 h " in fffc h ). it is advised to write the flash protection code at last. programming to the eprom with evaluation product device 1. eprom for use mbm27c256a (dip-28) 2. memory space. 3. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0000 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. 0000 h a ddress 0080 h 0280 h 8000 h ffff h 0000 h address 7fff h i/o normal operating mode ram 512 bytes not available prom 32 kbytes eprom 32 kbytes corresponding adresses on th e rom programmer
mb89202 series 14 block diagram x0 x1 rst p04 / int24 to p07 / int27 p00 / int20 / an4 to p03 / int23 / an7 p40 / an0* to p43 / an3* f 2 mc - 8 l cpu wild register 16 kbytes rom 512 bytes ram cmos i/o port (n-ch od) 10-bit a/d converter external interrupt2 (wake-up) cmos i/o port reset circuit clock controller main clock oscillator port 4 port 0 v cc , v ss , c 12-bit ppg buzzer output cmos i/o port exernal interrupt 1 8/16-bit capture timer/ counter 8-bit serial i/o 8-bit pwm cmos i/o port time-base timer uart internal bus port 5 port 3 serial function switching uart prescaler p37 / bz / ppg p35 / int11, p36 / int12 p34 / to / int1 0 p33 / ec p32 / ui / si p31 / uo / so p30 / uck / sc k p50 / pwm 4 32 4 4 4 8 4 other pins cmos i/o port port 6 2 p60 ,p61 cmos i/o port port 7 3 p70* to p72* * : large-current drive type
mb89202 series 15 cpu core 1. memory space the microcontrollers of the mb89202 se ries offer a memory space of 64 kbyt es for storing all of i/o, data, and program areas. the i/o area is located at the lowest addr ess. the data area is provided immediately above the i/o area. the data area can be divided in to register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the hi ghest address. provide the tables of interrupt reset vectors and vector call instructions to ward the highest address within the program area. the memory space of the mb89202 series is structured as illustrated below. i/o ram 512 bytes mb89202 mb89f202 mb89v201 ram 512 bytes ram 512 bytes not available not available not available external eprom 32 kbytes register register register rom 16 kbytes flash 16 kbytes i/o i/o 0000 h 0080 h 0100 h 0200 h 0280 h c 000 h f fff h 0000 h 0080 h 0100 h 0200 h 0280 h c000 h ffff h 0000 h 0080 h 0100 h 0200 h 0280 h 8000 h ffff h memory space
mb89202 series 16 2. registers the mb89202 series has two types of registers; dedicated registers in t he cpu and general-purpose registers in the memory. the following dedicated registers are provided : program counter (pc) : a 16-bit register for indicating instruction storage positions accumulator (a) : a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t) : a 16-bit register which performs arithmetic operati ons with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer for indicating a memory address stack pointer (sp) : a 16-bit register for indicating a stack area program status (ps) : a 16-bit register fo r storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr) . (see the diagram below.) ps pc 16 bits a t ix ep sp rp ccr : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h undefined undefined undefined undefined undefined i-flag = 0, il1, 0 = 11 the other bit values are undefined. initial value p s rp ccr x011xxxx b ccr initial valu e bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r4 r3 r2 r1 r0 ??? h i il1 il0 n z v c h-flag n-flag il1,0 i-flag z-flag c-flag v-flag : undefined structure of the program status register
mb89202 series 17 the rp indicates the address of the register bank curre ntly in use. the relationshi p between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of ar ithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag : set to ?1? when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i-flag : interrupt is enabled when this fl ag is set to ?1?. interrupt is disabl ed when the flag is cleared to ?0?. cleared to ?0? at the reset. il1, 0 : indicates the level of the interrupt currently allo wed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag : set to ?1? if the msb become s to ?1? as the result of an arithmet ic operation. cleared to ?0? when the bit is cleared to ?0?. z-flag : set to ?1? when an arithmetic opera tion results in 0. cleared to ?0? otherwise. v-flag : set to ?1? if the complement on 2 overflows as a result of an arithmetic operation. cleared to ?0? if the overflow does not occur. c-flag : set to ?1? when a carry or a borrow from bit 7 occu rs as a result of an arithm etic operation. cleared to ?0? otherwise. set to the shift-out valu e in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low = no interrupt 01 10 2 11 3 "0" "0" "0" "0" "0" "0" "0" "1" r4 r3 r2 r1 r0 b2 b1 rp lower op codes b0 a7 a6 a5 a4 a3 a2 a1 a 0 a15 g enerated addresses a14 a13 a12 a11 a10 a9 a8 rule for conversion of actual addresses of the general-purpose register area
mb89202 series 18 the following general-purpose registers are provided : general-purpose registers : an 8-bit register for storing data the general-purpose registers are 8 bits and located in t he register banks of the memory. one bank contains eight registers and up to a total of 16 banks can be us ed on the mb89202 series. the bank currently in use is indicated by the register bank pointer (rp) . r0 r1 r2 r3 r4 r5 r6 r7 16 bank s t his address = 0100 h + 8 (rp) memory area register bank configuration
mb89202 series 19 i/o map (continued) address register name register description read/write initial value 0000 h pdr0 port 0 data register r/w x x x x x x x x 0001 h ddr0 port 0 data direction register w 0 0 0 0 0 0 0 0 0002 h to 00006 h reserved 0007 h sycc system clock control register r/w 1 - - m m 1 0 0 0008 h stbc standby control register r/w 0 0 0 1 0 - - - 0009 h wdtc watchdog timer control register r/w 0 - - - x x x x 000a h tbtc time-base timer control register r/w 0 0 - - - 0 0 0 000b h reserved 000c h pdr3 port 3 data register r/w x x x x x x x x 000d h ddr3 port 3 data direction register w 0 0 0 0 0 0 0 0 000e h rsfr reset flag register r x x x x - - - - 000f h pdr4 port 4 data register r/w - - - - x x x x 0010 h ddr4 port 4 data direction register r/w - - - - 0 0 0 0 0011 h out4 port 4 output format register r/w - - - - 0 0 0 0 0012 h pdr5 port 5 data register r/w - - - - - - - x 0013 h ddr5 port 5 data direction register r/w - - - - - - - 0 0014 h rcr21 12-bit ppg control register 1 r/w 0 0 0 0 0 0 0 0 0015 h rcr22 12-bit ppg control register 2 r/w - - 0 0 0 0 0 0 0016 h rcr23 12-bit ppg control register 3 r/w 0 - 0 0 0 0 0 0 0017 h rcr24 12-bit ppg control register 4 r/w - - 0 0 0 0 0 0 0018 h bzcr buzzer register r/w - - - - - 0 0 0 0019 h tccr capture control register r/w 0 0 0 0 0 0 0 0 001a h tcr1 timer 1 control register r/w 0 0 0 - 0 0 0 0 001b h tcr0 timer 0 control register r/w 0 0 0 0 0 0 0 0 001c h tdr1 timer 1 data register r/w x x x x x x x x 001d h tdr0 timer 0 data register r/w x x x x x x x x 001e h tcph capture data register h r x x x x x x x x 001f h tcpl capture data register l r x x x x x x x x 0020 h tcr2 timer output control register r/w - - - - - - 0 0 0021 h reserved 0022 h cntr pwm control register r/w 0 - 0 0 0 0 0 0 0023 h comr pwm compare register w x x x x x x x x 0024 h eic1 external interrupt 1 control register 1 r/w 0 0 0 0 0 0 0 0
mb89202 series 20 (continued) address register name register description read/write initial value 0025 h eic2 external interrupt 1 control register 2 r/w - - - - 0 0 0 0 0026 h reserved 0027 h 0028 h smc serial mode control register r/w 0 0 0 0 0 - 0 0 0029 h src serial rate control register r/w - - 0 1 1 0 0 0 002a h ssd serial status and data register r/w 0 0 1 0 0 - 1 x 002b h sidr serial input data register r x x x x x x x x sodr serial output data register w x x x x x x x x 002c h upc clock division selection register r/w - - - - 0 0 1 0 002d h to 002f h reserved 0030 h adc1 a/d converter control register 1 r/w - 0 0 0 0 0 0 0 0031 h adc2 a/d converter control register 2 r/w - 0 0 0 0 0 0 1 0032 h addh a/d converter data register h r - - - - - - x x 0033 h addl a/d converter data register l r x x x x x x x x 0034 h aden a/d enable register r/w 0 0 0 0 0 0 0 0 0035 h reserved 0036 h eie2 external interrupt 2 control register1 r/w 0 0 0 0 0 0 0 0 0037 h eif2 external interrupt 2 control register2 r/w - - - - - - - 0 0038 h reserved 0039 h smr serial mode register r/w 0 0 0 0 0 0 0 0 003a h sdr serial data register r/w x x x x x x x x 003b h ssel serial function switching register r/w - - - - - - - 0 003c h to 003f h reserved 0040 h wrarh0 upper-address setting register r/w x x x x x x x x 0041 h wrarl0 lower-address setting register r/w x x x x x x x x 0042 h wrdr0 data setting register 0 r/w x x x x x x x x 0043 h wrarh1 upper-address setting register r/w x x x x x x x x 0044 h wrarl1 lower-address setting register r/w x x x x x x x x 0045 h wrdr1 data setting register 1 r/w x x x x x x x x 0046 h wren address comparison en register r/w x x x x x x 0 0 0047 h wror wild-register data test register r/w - - - - - - 0 0 0048 h to 005f h reserved
mb89202 series 21 (continued) - : unused, x : undefined, m : set using the mask option * : no used in mb89f202 note : do not use prohibited areas. address register name register description read/write initial value 0060 h pdr6 port 6 data register r/w - - - - - - x x 0061 h ddr6 port 6 data direction register* r/w - - - - - - 0 0 0062 h pul6 port 6 pull-up setting register r/w - - - - - - 0 0 0063 h pdr7 port 7 data register r/w - - - - - x x x 0064 h ddr7 port 7 data direction register r/w - - - - - 0 0 0 0065 h pul7 port 7 pull-up setting register r/w - - - - - 0 0 0 0066 h to 006f h reserved 0070 h pul0 port-0 pull-up setting register r/w 0 0 0 0 0 0 0 0 0071 h pul3 port-3 pull-up setting register r/w 0 0 0 0 0 0 0 0 0072 h pul5 port-5 pull-up setting register r/w - - - - - - - 0 0073 h to 0078 h reserved 0079 h fmcs flash memory control status register r/w 0 0 0 x - - - - 007a h reserved 007b h ilr1 interrupt level setting register1 w 1 1 1 1 1 1 1 1 007c h ilr2 interrupt level setting register2 w 1 1 1 1 1 1 1 1 007d h ilr3 interrupt level setting register3 w 1 1 1 1 1 1 1 1 007e h ilr4 interrupt level setting register4 w 1 1 1 1 1 1 1 1 007f h itr interrupt test register not available - - - - - - 0 0
mb89202 series 22 electrical characteristics 1. absolute maximum ratings * : this parameter is based on v ss = 0.0 v. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage* v cc v ss ? 0.3 v ss + 6.0 v input voltage* v i v ss ? 0.3 v cc + 0.3 v output voltage* v o v ss ? 0.3 v cc + 6.0 v ?l? level maximum output current i ol ? 15 ma ?l? level average output current i olav1 ? 4ma average value (operating current operating rate) pins excluding p40 to p43, p70 to p72 i olav2 ? 12 ma average value (operating current operating rate) pins p40 to p43, p70 to p72 ?l? level total maximum output current i ol ? 100 ma ?h? level maximum output current i oh ?? 10 ma pins excluding p60, p61 ?h? level average output current i ohav ?? 4ma average value (operating current operating rate) ?h? level total maximum output current i oh ?? 50 ma power consumption pd ? 200 mw operating temperature ta ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb89202 series 23 2. recommended operating conditions (vss = 0.0v) parameter symbol value unit remarks min max power supply voltage v cc 2.2 5.5 v mb89202 3.5 5.5 v mb89f202 2.7 5.5 v mb89v201 1.5 5.5 v retains the ram state in stop mode ?h? level input voltage v ih 0.7 v cc v cc + 0.3 v p00 to p07, p31, p37, p40 to p43, p50, p60, p61, p70 to p72 v ihs 0.8 v cc v cc + 0.3 v rst , ec, int20 to int27 , uck/sck, int10 to int12, p30, p32 to p36, ui/si ?l? level input voltage v il v ss ? 0.3 0.3 v cc v p00 to p07, p31, p37, p40 to p43, p50, p60, p61, p70 to p72 v ils v ss ? 0.3 0.2 v cc v rst , ec, int20 to int27 , uck/sck, int10 to int12, p30, p32 to p36, ui/si open-drain output pin application voltage v d v ss ? 0.3 v cc + 0.3 v p40 to p43, rst operating temperature ta ? 40 + 85 c room temperature is recommended for programming the flash memory on mb89f202
mb89202 series 24 warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. 6 5 4 3 2 1 1 10 3 2 05 operating frequency (mhz) 7 6 analog accuracy assurance range operation assurance range operating voltage (v) 9 8 4 12.5 11 2.2 2.7 3.5 4.5 5.5 operating assurance for mb89202 and mb89v201 : area is assured onl y for the mb89202 6 5 4 3 2 1 1 10 3 2 05 operating frequency (mhz) 7 6 operation assurance range operating voltage (v) 9 8 4 12.5 11 operating assurance for mb89f202 3.5 5.5 analog accuracy assurance range 4.5
mb89202 series 25 3. dc characteristics (v cc = 5.0 v 10 % , v ss = 0.0 v, f ch = 12.5 mhz (external clock) , ta = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max ?h? level input voltage v ih p00 to p07, p31, p37, p40 to p43, p50, p60, p61, p70 to p72 ? 0.7 v cc ? v cc + 0.3 v v ihs p30, p32 to p36, rst uck/sck, ui/si, ec, int20 to int27 , int10 to int12 ? 0.8 v cc ? v cc + 0.3 v ?l? level input voltage v il p00 to p07, p31, p37, p40 to p43, p50, p60, p61, p70 to p72 ? v ss ? 0.3 ? 0.3 v cc v v ils p30, p32 to p36, rst , uck/sck, ui/si, ec, int20 to int27 , int10 to int12 ? v ss ? 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p40 to p43, rst ? v ss ? 0.3 ? v cc + 0.3 v ?h? level output voltage v oh p00 to p07, p30 to p37, p40 to p43, p50, p70 to p72 i oh = ? 4.0 ma 4.0 ?? v ?l? level output voltage v ol1 p00 to p07, p30 to p37, p50, rst i ol = 4.0 ma ?? 0.4 v v ol2 p40 to p43, p70 to p72 i ol = 12.0 ma ?? 0.4 v input leakage current i li p00 to p07, p30 to p37, p40 to p43, p50 , p60, p61, rst , p70 to p72 0.45 v < v i < v cc ?? 5 a without pull-up resistor pull-up resistance r pull p00 to p07, p30 to p37, p50, rst , p70 to p72 v i = 0.0 v 25 50 100 k ? mb89202 p00 to p07, p30 to p37, p50, p70 to p72 mb89f202
mb89202 series 26 (continued) parameter sym- bol pin name condition value unit remarks min typ max power supply current i cc v cc normal operation mode (external clock, highest gear speed) when a/d converter stops ? 8 12 ma mb89202 ? 6 9 ma mb89f202 when a/d converter starts ? 10 15 ma mb89202 ? 8 12 ma mb89f202 i ccs sleep mode (external clock, highest gear speed) when a/d converter stops ? 4 6 ma mb89202 ? 3 5 ma mb89f202 i cch stop mode ta = + 25 c (external clock) when a/d converter stops ?? 1 a mb89202 ?? 10 a mb89f202 input capacitance c in other than c, v cc , v ss ?? 10 ? pf
mb89202 series 27 4. ac characteristics (1) reset timing (v ss = 0.0 v, ta = ? 40 c to + 85 c) * : t hcyl 1 oscillating clock cycle time notes: ? when the power-on reset option is not on, leave the ex ternal reset on until oscillation becomes stable. ? if the reset pulse applied to the external reset pin (rst ) does not meet the spec ifications, it may cause malfunctions. use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (rst ). (2) power-on reset (v ss = 0.0 v, ta = ? 40 c to + 85 c) note : the supply voltage must be set to the minimum val ue required for operation within the prescribed default oscillation settling time. parameter symbol condition value unit remarks min max rst ?l? pulse width t zlzh ? 45 ? ns internal reset pulse extension t irst ? 48 t hcyl * ? ns parameter symbol condition value unit remarks min max power supply rising time t r ? ? 50 ms power supply cut-off time t off 1 ? ms due to repeated operations r st 0.2 v cc 0.2 v cc t zlzh 0.8 v cc t irst i nternal r eset s ignal v cc t r 3.5 v 0.2 v 0.2 v 0.2 v t off
mb89202 series 28 (3) clock timing (v ss = 0.0 v, ta = ?40 c to +85 c) (4) instruction cycle parameter symbol condition value unit remarks min max clock frequency f ch ? 1 12.5 mhz clock cycle time t xcyl 80 1000 ns input clock pulse width t wh t wl 20 ? ns input clock rising/falling time t cr t cf ? 10 ns parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch s t inst = 0.32 s when operating at f ch = 12.5 mhz (4/f ch ) t xcyl t wh t cr t cf t wl 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc x 0 x0 x1 x0 x1 w hen a crystal or ceramic resonator is used when an exerna l clock is used open x0 and x1 timing and conditions main clock conditions
mb89202 series 29 (5) peripheral input timing (v cc = 5.0 v 10 % , v ss = 0.0 v, ta = ? 40 c to + 85 c) * : for information on t inst see ? (4) instruction cycle?. (v cc = 5.0 v 10 % , v ss = 0.0 v, ta = ? 40 c to + 85 c) parameter symbol pin name value unit remarks min max peripheral input ?h? pulse width t ilih int10 to int12, int20 to int27 , ec 2 t inst * ? s peripheral input ?l? pulse width t ihil 2 t inst * ? s parameter symbol pin name value unit remarks min typ max peripheral input ?h? noise limit t ihnc p00 to p07, p30 to p37, p40 to p43, p50,p60,p61, p70 to p72, rst , ec, int20 to int27 , int10 to int12 ? 45 ? ns peripheral input ?l? noise limit t ilnc ? 45 ? ns i nt10 to int12, i nt20 to int27, ec t ilih t ihil 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t ihnc t ilnc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc p 00 to p07, p30 to p37, p 40 to p43, p50, p 60, p61, p70 to p72, r st, ec, int20 to int27, i nt10 to int12
mb89202 series 30 (6) uart, serial i/o timing (v cc = 5.0 v 10 % , v ss = 0.0 v, ta = ? 40 c to + 85 c) * : for information on t inst , see ? (4) instruction cycle?. parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc uck/sck internal shift clock mode 2 t inst * ? s uck/sck so time t slov uck/sck, so ? 200 200 ns valid si uck/sck t ivsh uck/sck, si 1/2 t inst * ? s uck/sck valid si hold time t shix uck/sck, si 1/2 t inst * ? s serial clock ?h? pulse width t shsl uck/sck external shift clock mode t inst * ? s serial clock ?l? pulse width t slsh uck/sck t inst * ? s uck/sck so time t slov uck/sck, so 0 200 ns valid si uck/sck t ivsh uck/sck, si 1/2 t inst * ? s uck/sck valid si hold time t shix uck/sck, si 1/2 t inst * ? s internal shift clock mode external shift clock mode u ck/sck s o s i t scyc t ivsh t slov t shix 0.8 v 0.8 v 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 2.4 v u ck/sck s o s i t ivsh t slov t shix 0.2 v cc 0.2 v cc 0.8 v 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slsh t shsl
mb89202 series 31 5. a/d converter (1) a/d converter electrical characteristics (v ss = 0.0 v, ta = ? 40 c to + 85 c) * : for information on t inst , see ? (4) instruction cycle? in ?4. ac characteristics.? parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 5.0 ?+ 5.0 lsb linearity error ? 3.0 ?+ 3.0 lsb differential linearity error ? 2.5 ?+ 2.5 lsb zero transition voltage v ot v ss ? 3.5 lsb v ss + 0.5 lsb v ss + 4.5 lsb v full-scale transition voltage v fst v cc ? 6.5 lsb v cc ? 1.5 lsb v cc + 2.0 lsb v a/d mode conversion time ?? ? 38 t inst * s analog port input current i ain ?? 10 a analog input voltage range ? 0 ? v cc v power supply voltage for a/d accuracy assurance v cc 4.5 ? 5.5 v
mb89202 series 32 (2) a/d converter glossary resolution analog changes that are identif iable with the a/d converter when the number of bits is 10, anal og voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation of the straight line connecti ng the zero transition point (?00 0000 0000? ? ?00 0000 0001?) with the full-scale transition point (?11 1111 1111? ? ?11 1111 1110?) from actual conversion characteristics differential linearity error (unit : lsb) the deviation of input voltage needed to change the out put code by 1 lsb from the theoretical value total error (unit : lsb) the difference between theoretical and actual conversion values (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss v c c v ot 0.5 lsb 1 lsb theoretical i/o characteristics analog input digital output 1.5 lsb v fst 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss v c c v nt {1 lsb n + 0.5 lsb} actual conversion value actual conversion value theoretical value total error analog input digital output 004 h 003 h 002 h 001 h av ss actual conversion value theoretical conversion value actual conversion value v ot (measured value) zero transition error analog input digital output 3ff h 3fe h 3fd h 3fc h v c c theoretical value actual conversion value v fst (measured value) actual conversion value full-scale transition error analog input digital output 1 lsb = v fst ? v ot 1022 (v) total error of digital output n = v nt ? {1 lsb n + 0.5 lsb} 1 lsb
mb89202 series 33 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss v nt v c c {1 lsb n + v ot } actual conversion value v fst (measured value) actual conversion value theoretical conversion value v ot (measured value) linearity error analog input digital output n + 1 n n ? 1 n ? 2 av ss v c c v nt theoretical conversion value actual conversion value actual conversion value v (n + 1) t differential linearity error analog input digital output ? 1 differential linearity error of digital output n = v ( n + 1 ) t ? v nt 1 lsb linearity error of digital output n = v nt ? {1 lsb n + v ot } 1 lsb
mb89202 series 34 (3) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. if the sampling time cannot be suffici ent, connect a capacitor of about 0.1 f to the analog input pin. about errors as |v cc ? av ss | becomes smaller, values of relative errors grow larger. r c analog input circuit model analog input comparator during sampling : on r 2.2 k ? (max) 2.0 k ? (max) c 45 pf (max) 16 pf (max) note : the values are reference values. mb89202 mb89f202 1 00 90 80 70 60 50 40 30 20 10 0 35 30 25 20 15 10 5 0 0 1 2 34 5 6 7 8 0 2 4 6 8 10 12 14 16 18 20 the relationship between the external impedance and minimum sampling time minimum sampling time ( s) minimum sampling time ( s) external impedance (k ? ) external impedance (k ? ) [external impedance = 0 k ? to 100 k ? ] [external impedance = 0 k ? to 20 k ? ] mb89202 mb89f202 mb89202 mb89f202
mb89202 series 35 6. mb89f202 flash memory program / erase characteristics *1: ta = + 25 c, vcc = 3.0 v, 10,000 cycles *2: ta = + 85 c, vcc = 2.7 v, 10,000 cycles parameter value unit remarks min typ max chip erase time (16 kb) ? 0.5 *1 7.5 *2 s excludes programming prior to erasure byte programming time ? 32 3600 s excludes system-level overhead program / erase cycle 10,000 ?? cycle
mb89202 series 36 example characteristics 1. power supply current mb89202/f202 : 4 mhz (when external clock are used) 0.0 1.0 2.0 3.0 1234567 i cc (ma) (f ch = 4 mhz, ta = +25 ?c) v cc (v) 0.0 1.0 2.0 3.0 4.0 1234567 i cc (ma) v cc (v) (f ch = 4 mhz, ta = +25 ?c) i cc 1 (gear : 4 divide) i cc 2 (gear : 64 divide) i cc 1 (gear : 4 divide) i cc 2 (gear : 64 divide) 0.0 0.5 1.0 1.5 1234567 i ccs (ma) (f ch = 4 mhz, ta = +25 ?c) v cc (v) 0.0 0.5 1.0 1.5 1234567 i ccs (ma) v cc (v) (f ch = 4 mhz, ta = +25 ?c) i ccs 1 (gear : 4 divide) i ccs 2 (gear : 64 divide) i ccs 1 (gear : 4 divide) i ccs 2 (gear : 64 divide) mb89202 normal operation mode (i cc 1 ? v cc , i cc 2 ? v cc ) mb89202 sleep mode (i cc s1 ? v cc , i cc s2 ? v cc ) mb89f202 normal operation mode (i cc 1 ? v cc , i cc 2 ? v cc ) mb89f202 sleep mode (i cc s1 ? v cc , i cc s2 ? v cc )
mb89202 series 37 mb89202/f202 : 8 mhz ( when external clock are used) v cc (v) (f ch = 8 mhz, ta = +25 ?c) i cc (ma) (f ch = 8 mhz, ta = +25 ?c) 0.0 1.0 2.0 3.0 4.0 5.0 1234567 v cc (v) 0.0 2.0 4.0 6.0 8.0 1234567 i cc (ma) i cc 1 (gear : 4 divide) i cc 2 (gear : 64 divide) i cc 1 (gear : 4 divide) i cc 2 (gear : 64 divide) 0.0 0.5 1.0 1.5 2.0 1234567 i ccs (ma) (f ch = 8 mhz, ta = +25 ?c) v cc (v) 0.0 0.5 1.0 1.5 2.0 2.5 1234567 i ccs (ma) v cc (v) (f ch = 8 mhz, ta = +25 ?c) i ccs 1 (gear : 4 divide) i ccs 2 (gear : 64 divide) i ccs 2 (gear : 64 divide) i ccs 1 (gear : 4 divide) mb89202 normal operation mode (i cc 1 ? v cc , i cc 2 ? v cc ) mb89202 sleep mode (i cc s1 ? v cc , i cc s2 ? v cc ) mb89f202 normal operation mode (i cc 1 ? v cc , i cc 2 ? v cc ) mb89f202 sleep mode (i cc s1 ? v cc , i cc s2 ? v cc )
mb89202 series 38 mb89202/f202 : 12.5 mhz (when external clock is used) mb89202 normal operation mode (i cc 1 ? v cc , i cc 2 ? v cc ) mb89f202 normal operation mode (i cc 1 ? v cc , i cc 2 ? v cc ) mb89202 sleep mode (i cc s1 ? v cc , i cc s2 ? v cc ) mb89f202 sleep mode (i cc s1 ? v cc , i cc s2 ? v cc ) 0.0 0.5 1.0 1.5 2.0 1234567 i cc s (ma) v cc (v) (f ch = 12.5 mhz, ta = +25 ?c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1234567 i cc s (ma) v cc (v) (f ch = 12.5 mhz, ta = +25 ?c) i ccs 1 (gear : 4 divide) i ccs 2 (gear : 64 divide) i ccs 2 (gear : 64 divide) i ccs 1 (gear : 4 divide) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 1234567 i cc (ma) v cc (v) (f ch = 12.5 mhz, ta = +25 ?c) 0.0 1.0 2.0 3.0 4.0 5.0 1234567 i cc (ma) v cc (v) (f ch = 12.5 mhz, ta = +25 ?c) i cc 1 (gear : 4 divide) i cc 2 (gear : 64 divide) i cc 2 (gear : 64 divide) i cc 1 (gear : 4 divide)
mb89202 series 39 mb89202/f202 : 12.5 mhz (when external clock is used) mb89202 stop mode (i cch ? ta) mb89f202 stop mode (i cch ? ta) i cch ( a) (f ch = 12.5 mhz, v cc = 5.5 v ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -15 10 35 60 8 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -15 10 35 60 85 i cch ( a) (f ch = 12.5 mhz, v cc = 5.5 v) ta ( c) ta ( c)
mb89202 series 40 2. ?l? level output voltage 3. ?h? level output voltage 0.6 0.5 0.4 0.3 0.2 0.1 0.0 4681012 16 14 v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 6.0 v v ol (v) i ol2 (ma) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 123456 v ol (v) i ol1 (ma) v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 6.0 v mb89202 v ol vs. i ol1 mb89202 v ol vs. i ol2 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 v cc ? v oh (v) i oh (ma) v cc = 2.0 v v cc = 2.5 v v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 6.0 v mb89202 (v cc ? v oh ) vs. i oh
mb89202 series 41 mask options f ch : main clock oscillation frequency * : initial value to which the oscillation settling time bit (sycc : wt1, wt0) in the system clock control register is set note notes on selecting mask option please select ?with reset output? by the mask option when power-on reset is generated at the power supply on, and the device is used without inputting external reset. ordering information no. part number mb89202 mb89f202 mb89v201 specifying procedure specify when ordering masking specify by part number 1 selection of initial value of main clock oscillation settling time* (with f ch = 12.5 mhz) 01 : 2 14 /f ch (approx.1.31 ms) 10 : 2 17 /f ch (approx.10.5 ms) 11 : 2 18 /f ch (approx.21.0 ms) selectable fixed to 2 18 /f ch fixed to 2 18 /f ch 2 reset pin output with reset output without reset output selectable with reset output with reset output 3 power on reset selection with power on reset without power on reset selectable with power on reset with power on reset part number package remarks MB89202P-SH 32-pin plastic sh-dip (dip-32p-m06) mb89f202p-sh mb89202pfv 34-pin plastic ssop (fpt-34p-m03) mb89f202pfv mb89v201pfv 64-pin plastic lqfp (fpt-64p-m03)
mb89202 series 42 package dimensions (continued) 32-pin plastic sh-dip (dip-32p-m06) c 2003 fujitsu limited d32018s-c-1-1 (.350 .010) *8.89 0.25 1.778(.070) 1.27(.050) 10.16(.400) index *28.00 1.102 +0.20 ? 0.30 ? .012 +.008 4.70 .185 +0.70 ? 0.20 ? .008 +.028 3.30 .130 +0.20 ? 0.30 ? .012 +.008 max. 1.02 .040 ? 0.20 ? .008 +.012 +0.30 min. 0.51(.020) 0~15? m 0.25(.010) .019 0.48 +0.08 +.003 ? .005 ? 0.12 0.27 .011 ? .003 ? 0.07 +.001 +0.03 dimensions in mm (inches). note: the values in parent heses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thi ckness include plating thickness.
mb89202 series 43 (continued) 34-pin plastic ssop (fpt-34p-m03) c 2003 fujitsu limited f34003s-c-2-3 11.000.10(.433.004) 6.100.10 8.100.20 (.240.004) (.319.008) "a" .009 ? .003 +.003 ? 0.07 +0.08 0.24 index 0.10(.004) m 0.10(.004) 0.10(.004) * 1 * 2 (.007.001) 0.170.03 0.25(.010) 0.100.10 (.004.004) (stand off) details of "a" part (mounting height) 1.25 +0.20 ?0.10 ?.004 +.008 .049 0~8 ? 0.500.20 (.020.008) 0.600.15 (.024.006) 1 17 34 18 0.65(.0265) dimensions in mm (inches). note: the values in parent heses are reference values note 1) * 1 : resin protrusion. (each side : +0.15 (.006) max). note 2) * 2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder.
mb89202 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0503 ? 2005 fujitsu limited printed in japan

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